Figure 1 presents a block diagram of the VSP E1090 dual-controller system. Each interface board (CHB, DKBN) is connected to a controller using 8 x PCIe Gen 3 lanes, which means 16 GB/s of available bandwidth (8 GB/s send, and 8 GB/s receive). The configuration in Figure 1 includes two pairs of NVMe disk adapters (DKBNs) that support 1-2 NVMe drive boxes (DBNs) and up to 48 NVMe SSDs. Each controller in this configuration has up to 96 GB/s of front-end theoretical bandwidth (if six CHBs per controller were configured), and 32 GB/s of back end bandwidth (two DKBNs). An alternative configuration (not pictured) doubles the capability of the NVMe back end, with four DKBNs per controller supporting 3-4 DBNs and up to 96 NVMe SSDs. The latter configuration would have 64 GB/s of back end bandwidth per controller and up to 64 GB/s of front-end bandwidth per controller (if 4 CHBs per controller were installed).
Like previous Hitachi enterprise products, all VSP E1090 processors run a single SVOS image and share a global cache. Cache is distributed across individual controllers for fast, efficient, and balanced memory access. Although VSP E1090 hardware and microcode would permit a variety of cache configurations, the only configuration available has the maximum cache configuration (1 TB). Therefore, all eight DIMM slots per controller are populated with 64 GB DDR4-2400 DIMMs for a total of 153.6 GB/s of theoretical memory bandwidth per controller.
ADR performance was improved up to 2X by the addition of 2 Compression Accelerator Modules per controller. The compression accelerators are labeled “ACLF” in Figure 1. As observed in GPSE testing, the compression accelerator improves ADR performance as much as 2X, while also boosting capacity savings. The Compression Accelerator Module allows the CPU to offload the work of compression to a Hitachi-designed ASIC (application-specific integrated circuit). The ASIC uses an efficient compression algorithm optimized for implementation in specialized hardware. The compression accelerator operates on data in cache using direct memory addressing (DMA); it does not require copy operations and can perform work with very low latency. As shown in Figure 2, the Compression Accelerator Module is connected to the controller using eight PCI Express Gen3 lanes. Within the accelerator module, a PCIe switch connects four lanes to each of the two ASICs per Compression Accelerator Module. The compression accelerator occupies unused space in the fan module (two per controller), so each controller gets four compression ASICs.